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max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection ????????????????????????????????????????????????????????????????? maxim integrated products 1 19-5950; rev 0; 6/11 typical operating circuit ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/max7370.related . general description the max7370 i 2 c-interfaced peripheral provides micro - processors with management of up to 64 key switches, with optional gpio and pwm-controlled led drivers. the key-switch drivers interface with metallic or resistive switches with on-resistances up to 5k i . key inputs are monitored statically, not dynamically, to ensure low-emi operation. the ic features autosleep and autowake modes to further minimize the power consumption of the device. the autosleep feature puts the device in a low-power state (1a typ) after a timeout period. the autowake feature configures the device to return to normal operating mode from sleep upon a keypress. the key controller debounces and maintains a fifo buffer of keypress and release events (including auto - repeat, if enabled). an interrupt ( int ) output can be configured to alert keypresses, as they occur, or at the maximum rate. the same index rows and columns in the device can be used as a direct logic-level translator. if the device is not used for key-switch control, all keyboard pins can be used as gpios. each gpio can be programmed to one of the two externally applied logic voltage levels. four column ports (col7Ccol4) can also be configured as led drivers that feature constant-current and pwm intensity control. the maximum constant-current level for each open-drain led port is 20ma. the intensity of the led on each open-drain port can be individually adjusted through a 256-step pwm control. the device is offered in a 24-pin (3.5mm x 3.5mm) tqfn package with an exposed pad, and small 25-bump (2.159mm x 2.159mm) wafer-level package (wlp) for cell phones, pocket pcs, and other portable consumer electronic applications. the device operates over the -40c to +85c extended temperature range. applications cell phones notebooks pdas handheld games portable consumer electronics features s monitors up to 64 keys s integrated high-esd protection 8kv iec 61000-4-2 contact discharge 14kv iec 61000-4-2 air-gap discharge s keyscan uses static matrix monitoring for low-emi operation s four led driver pins on col7Ccol4 s 5v tolerant, open-drain i/o ports capable of constant-current led drive s 256-step pwm individual led intensity-control accuracy s individual led blink rates and common led fade in/out rates from 256ms to 4096ms s fifo queues up to 16 debounced key events s user-configurable keypress and release debounce time (2ms to 32ms) s key-switch interrupt ( int ) on each debounced event/fifo level, or end-of-definable time period s 1.62v to 3.6v operating supply voltage s individually programmable gpios to two logic levels s 8-channel individual programmable level translators s provides optional gpios on all row ? and col? pins s supports hot insertion s 400kbps, 5.5v tolerant i 2 c serial interface with selectable bus timeout e v a l u a t i o n k i t a v a i l a b l e +5v +1.8v v cc +2.6v v la col[0:3] 32 keys 4 row[0:7] 8 gnd col4 col5 col6 col7 i/o i/o sda scl ad0 mcu max7370 int for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection v cc , v la to gnd .................................................... -0.3v to +4v col3Ccol0, row7Crow0 to gnd ....... -0.3v to (v cc + 0.3v) col7Ccol4 to gnd ............................................... -0.3v to +6v sda, scl, ad0, int to gnd .................................. -0.3v to +6v v la to v cc ........................................................... -0.3v to +2.3v dc current on col7Ccol4 to gnd ................................. 25ma dc current on col3Ccol0, row7Crow0 to gnd ........... 7ma v cc , v la , gnd current ..................................................... 80ma dc current v cc , v la to col3Ccol0, row7Crow0 ......... 5ma continuous power dissipation (t a = +70c) 24-pin tqfn (derate 15.4mw/c above +70c) ...... 1229mw 25-bump wlp (derate 19.2mw/c above +70c) ...... 850mw operating temperature range .......................... -40c to +85c junction temperature ..................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (tqfn) (soldering, 10s) ................... +300c soldering temperature (reflow) ...................................... +260c 24 tqfn junction-to-ambient thermal resistance ( b ja ) ......... 65.1c/w junction-to-case thermal resistance ( b jc ) ................ 5.4c/w 25 wlp junction-to-ambient thermal resistance ( b ja ) ........... 52c/w absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v cc = 1.62v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c.) (notes 2, 3) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units operating supply voltage v cc 1.62 3.3 3.6 v second logic supply v la v cc 3.3 3.6 v operating supply current i cc all key switches open, oscillator running 50 65 f a n keys pressed 50 + 28 o n sleep-mode supply current i sl not using gpo or led configuration 1.8 3 f a por threshold v por 1.2 v key-switch specifications key-switch source current i key 28 40 f a key-switch source voltage v key 0.45 0.5 v key-switch resistance r key (note 4) 5 k i startup time from sleep t start 2 2.7 ms gpio specifications external supply voltage col7Ccol4 (led drivers) v led 5 v led port-to-port sink current variation v cc = 3.3v, v ol = 1v, t a = +25 n c, 10ma output mode q 1.5 q 2.4 %
????????????????????????????????????????????????????????????????? maxim integrated products 3 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection electrical characteristics ( continued ) (v cc = 1.62v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units 10ma port sink current col7Ccol4 i ol v ol = 1v t a = +25 n c 8.6 11.4 ma v cc = 3.3v 9.04 10 10.96 v ol = 0.5v v cc = 3.6v, t a = +25 n c 9.5 20ma port sink current col7Ccol4 i ol v ol = 1v t a = +25 n c 18.13 21.52 ma v cc = 3.3v 18.47 20 21.34 v ol = 0.5v v cc = 3.6v, t a = +25 n c 19.05 input high voltage col_, row_ v ih v s = v cc or v la depending on reference logic level setting 0.7 o v s v input low voltage col_, row_ v il 0.3 o v s v input leakage current col3Ccol0, row_ i leakage input voltage = v cc or v gnd -2 +2 f a input leakage current col7Ccol4 i leakage input voltage = 5v -1 +1 f a input capacitance col _, row_ c in 20 pf maximum allowable load capacitance for keyscan function n keys pressed simultaneously 500 pf output low voltage col_, row_ v ol v cc = 1.62v and i sink = 2.5ma 50 100 mv v cc = 1.62v and i sink = 5ma 80 250 output high voltage col3Ccol0, row_ v oh v cc = 1.62v and i source = 2.5ma v cc - 120 v cc - 40 mv v cc = 1.62v and i source = 5ma v cc - 250 v cc - 70 output logic-low voltage ( int ) v ol i sink = 6ma 0.6 v pwm frequency f pwm derived from oscillator clock 500 hz serial-interface specifications input high voltage sda, scl, ad0 v ih 0.7 o v cc v input low voltage sda, scl, ad0 v il 0.3 o v cc v input leakage current sda, scl, ad0 i leakage input voltage = 5.5v or v gnd -1 +1 f a output logic-low voltage sda v ol i sink = 6ma 0.6 v input capacitance sda, scl, ad0 c in (notes 4, 5) 10 pf
????????????????????????????????????????????????????????????????? maxim integrated products 4 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection electrical characteristics ( continued ) (v cc = 1.62v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c.) (notes 2, 3) note 2: all parameters are tested at t a = +25c. specifications over temperature are guaranteed by design. note 3: all digital inputs at v cc or gnd. note 4: guaranteed by design. note 5: c b = total capacitance of one bus line in pf. t r and t f measured between 0.8v and 2.1v. note 6: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scls falling edge. note 7: i sink = 6ma. c b = total capacitance of one bus line in pf. t r and t f measured between 0.8v and 2.1v. note 8: input filters on the sda, scl, and ad0 inputs suppress noise spikes less than 50ns. parameter symbol conditions min typ max units i 2 c timing specifications scl serial-clock frequency f scl bus timeout enabled 0.05 400 khz bus timeout disabled 0 400 bus free time between a stop and start condition t buf 1.3 f s hold time (repeated) start condition t hd, sta 0.6 f s repeated start condition setup time t su, sta 0.6 f s stop condition setup time t su, sto 0.6 f s data hold time t hd, dat (note 6) 0.9 f s data setup time t su, dat 100 ns scl clock low period t low 1.3 f s scl clock high period t high 0.7 f s rise time of both sda and scl signals, receiving t r (notes 4, 5) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 4, 5) 20 + 0.1c b 300 ns fall time of sda signal, transmitting t f, tx (notes 4, 7) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (notes 4, 8) 50 ns capacitive load for each bus line c b (note 4) 400 pf bus time out t timeout 14 19 27 ms esd protection row7Crow0, col7Ccol0 iec 61000-4-2 air-gap discharge q 14 kv iec 61000-4-2 contact discharge q 8 all other pins human body model q 1.5 kv
????????????????????????????????????????????????????????????????? maxim integrated products 5 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection typical operating characteristics (v cc = 2.5v, v la = 2.5v, t a = +25 n c, unless otherwise noted.) gpo output low voltage vs. sink current (col7?col4) max7370 toc01 sink current (ma) gpo output low voltage (mv) 18 16 14 12 10 8 6 4 2 20 40 60 80 100 120 0 0 20 v cc = 2.4v t a = +85c t a = +25c t a = -40c gpo output low voltage vs. sink current (col7?col4) max7370 toc02 sink current (ma) gpo output low voltage (mv) 18 16 14 12 10 8 6 4 2 20 40 60 80 100 120 0 0 20 v cc = 3.0v t a = +85c t a = +25c t a = -40c gpo output low voltage vs. sink current (col7?col4) max7370 toc03 sink current (ma) gpo output low voltage (mv) 18 16 14 12 10 8 6 4 2 20 40 60 80 100 120 0 0 20 v cc = 3.6v t a = +85c t a = +25c t a = -40c supply current vs. supply voltage max7370 toc04 supply voltage (v) supply current (a) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 35 40 45 50 55 60 30 1.6 3.6 autosleep = off t a = +85c t a = +25c t a = -40c key-switch source current vs. supply voltage max7370 toc05 supply voltage (v) key-switch source current (a) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 24.5 25.0 25.5 26.0 26.5 27.0 24.0 1.6 3.6 v col0 = 0v t a = +85c t a = +25c t a = -40c sleep-mode supply current vs. supply voltage max7370 toc06 supply voltage (v) sleep-mode supply current (a) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 3.6 t a = +85c t a = +25c t a = -40c constant-current gpio output sink current vs. output voltage (col7?col4) max7370 toc07 output voltage (v) constant-current gpio output sink current (ma) 2.5 2.0 1.5 1.0 0.5 5 10 15 20 25 0 0 3.0 v cc = 2.4v t a = +85c t a = +25c t a = -40c constant-current gpio output sink current vs. output voltage (col7?col4) max7370 toc08 output voltage (v) constant-current gpio output sink current (ma) 2.5 2.0 1.5 1.0 0.5 5 10 15 20 25 0 0 3.0 v cc = 3.0v t a = +85c t a = +25c t a = -40c constant-current gpio output sink current vs. output voltage (col7?col4) max7370 toc09 output voltage (v) constant-current gpio output sink current (ma) 2.5 2.0 1.5 1.0 0.5 5 10 15 20 25 0 0 3.0 v cc = 3.6v t a = +85c t a = +25c t a = -40c
????????????????????????????????????????????????????????????????? maxim integrated products 6 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection pin description pin configurations pin name function tqfn wlp 1 a2 row5 row 5 input from key matrix or gpio port 2 b2 row6 row 6 input from key matrix or gpio port 3 a3 row7 row 7 input from key matrix or gpio port 4 b3 col7 column 7 output from key matrix or open-drain gpio port. col7 can be configured as a constant-current sink. 5 a4 col6 column 6 output from key matrix or open-drain gpio port. col6 can be configured as a constant-current sink. 6 a5 col5 column 5 output from key matrix or open-drain gpio port. col5 can be configured as a constant-current sink. 7 b4 col4 column 4 output from key matrix or open-drain gpio port. col4 can be configured as a constant-current sink. 8, 23 b1, b5, c3 gnd ground 9 c5 col3 column 3 output from key matrix or gpio port 10 c4 col2 column 2 output from key matrix or gpio port 11 d5 col1 column 1 output from key matrix or gpio port 12 e5 col0 column 0 output from key matrix or gpio port max7370 top view (bump side down) a b c d wlp e 1 2 3 4 row4 row5 row7 col6 col5 gnd row6 col7 col4 gnd row3 row2 gnd col2 col3 row1 v cc sda v la col1 row0 scl ad0 col0 5 + int tqfn max7370 19 20 21 22 1 + 2 3 4 5 6 18 17 16 15 14 13 23 24 12 11 10 9 8 7 row0 row2 row1 row3 row4 row5 row6 row7 col7 col6 col5 v cc int sda ad0 v la gnd col0 *connect ep to ground. col2 col1 col3 col4 gnd scl top view ep*
????????????????????????????????????????????????????????????????? maxim integrated products 7 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection pin description (continued) functional block diagram pin name function tqfn wlp 13 d4 v la second logic level for gpio level shifting (where v cc p v la p 3.6v) 14 e4 ad0 address input. selects up to four device slave addresses (table 3). 15 d3 sda i 2 c-compatible, serial-data i/o 16 e3 scl i 2 c-compatible, serial-clock input 17 e2 int active-low key-switch interrupt output. int is open-drain and requires a pullup resistor. 18 d2 v cc positive supply voltage. bypass to gnd with a 0.1 f f capacitor as close as possible to the device. 19 e1 row0 row 0 input from key matrix or gpio port 20 d1 row1 row 1 input from key matrix or gpio port 21 c2 row2 row 2 input from key matrix or gpio port 22 c1 row3 row 3 input from key matrix or gpio port 24 a1 row4 row 4 input from key matrix or gpio port ep exposed pad (tqfn only). internally connected to gnd. connect to a large ground plane to maximize thermal performance. not intended as an electrical connection point. int 128khz oscillator control registers fifo bus timeout por key-scan logic row drives/ push- pull gpio pwm gpio logic row0 row1 row2 row3 row4 row5 row6 row7 col1 col2 col3 col4 col5 col6 col7 led enable i/o supply control i 2 c interface pwm signal v la v cc ad0 scl sda current source column drives/ push- pull gpio/ led drivers column enabl e gpio enable row detect gpio enable current detect gpio input row enable gpio input col0 max7370
????????????????????????????????????????????????????????????????? maxim integrated products 8 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection detailed description the max7370 is a microprocessor peripheral low-noise key-switch controller that monitors up to 64 key switches with optional autorepeat, and key events that are pre - sented in a 16-byte fifo. key-switch functionality can be traded to provide up to 16 logic inputs. the device also features 12 push-pull gpos configured for digital i/o and four open-drain gpos configurable as constant- current outputs for led applications up to 5v. the device supports a second 1.62v to 3.6v power supply for level translation. the second logic supply voltage (v la ) must be set equal to or higher than v cc . the device features an automatic sleep mode and auto - matic wakeup that further reduce supply current con - sumption. the device can be configured to enter sleep mode after a programmable time following a key event. the fifo content is maintained and can be read in sleep mode. the device does not enter autosleep when a key is held down. the autowake feature takes the device out of sleep mode following a keypress. autosleep and autowake are enabled/disabled by programming the configuration register (0x01). to prevent overloading the microprocessor with too many interrupts, interrupt requests can be triggered after a programmable number of fifo entries have been exceeded, and/or after a set period of time (0x05). the key-switch status is checked by reading the key-switch fifo. a 1-byte read access returns both the next key event in the fifo (if there is one) and the fifo status. up to four of the key-switch outputs function as open- drain gpos capable of driving additional leds when the application requires fewer keys to be scanned. for each key-switch output used as a gpo, the number of moni - tored key switches reduces by eight. the device meets esd requirements for 8kv contact dis - charge and 14kv air-gap discharge on all key-switch pins. initial power-up on power-up, all control registers are set to power-up values ( table 1 ) and the device is in sleep mode. table 1. register address map and power-up conditions address code (hex) read/write power-up value (hex) register function description 0x00 read only 0x3f keys fifo read fifo keyscan data out 0x01 r/ w 0x0b configuration power-down, key-release enable, autowake, and i 2 c timeout enable 0x02 r/ w 0xff debounce key debounce time setting 0x03 r/ w 0x00 interrupt key-switch interrupt and int frequency setting 0x05 r/ w 0x00 key repeat delay and frequency for key repeat 0x06 r/ w 0x07 sleep idle time to autosleep 0x30 r/ w 0xff key-switch size keyscan switch array size 0x31 r/ w 0x00 led driver enable led driver enable register 0x34 r/ w 0x00 gpio direction 1 gpio input/output control register 1 for row7Crow0 0x35 r/ w 0x00 gpio direction 2 gpio input/output control register 2 for col7Ccol0 0x36 r/ w 0xff gpo output mode 1 gpo open-drain/push-pull output setting for row7Crow0 0x37 r/ w 0x0f gpo output mode 2 gpo open-drain/push-pull output setting for col7Ccol0
????????????????????????????????????????????????????????????????? maxim integrated products 9 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 1. register address map and power-up conditions (continued) address code (hex) read/write power-up value (hex) register function description 0x38 r/ w 0x00 gpio supply voltage 1 gpio voltages supplied by v cc or v la for row7Crow0 0x39 r/ w 0x00 gpio supply voltage 2 gpio voltages supplied by v cc or v la for col7Ccol0 0x3a r/ w 0xff gpio values 1 debounced input or output values of row7Crow0 0x3b r/ w 0xff gpio values 2 debounced input or output values of col7Ccol0 0x3c r/ w 0x00 gpio level- shifter enable gpio direct level-shifter pair enable 0x40 r/ w 0x00 gpio global configuration gpio global enable, gpio reset, led fade enable 0x42 r/ w 0x00 gpio debounce row7Crow0 debounce time setting 0x43 r/ w 0xc0 led constant- current setting col7Ccol4 constant-current output setting 0x45 r/ w 0x00 common pwm common pwm duty-cycle setting 0x48 read only 0x00 i 2 c timeout flag i 2 c timeout since last por 0x50 r/ w 0x00 col4 pwm ratio col4 individual duty-cycle setting 0x51 r/ w 0x00 col5 pwm ratio col5 individual duty-cycle setting 0x52 r/ w 0x00 col6 pwm ratio col6 individual duty-cycle setting 0x53 r/ w 0x00 col7 pwm ratio col7 individual duty-cycle setting 0x54 r/ w 0x00 col4 led configuration col4 interrupt, pwm mode control, and blink- period settings 0x55 r/ w 0x00 col5 led configuration col5 interrupt, pwm mode control, and blink- period settings 0x56 r/ w 0x00 col6 led configuration col6 interrupt, pwm mode control, and blink- period settings 0x57 r/ w 0x00 col7 led configuration col7 interrupt, pwm mode control, and blink- period settings 0x58 r/ w 0xff interrupt mask 1 interrupt mask for row7Crow0 0x59 r/ w 0xff interrupt mask 2 interrupt mask for col7Ccol0 0x5a r/ w 0x00 gpi trigger mode 1 gpi edge-triggered detection setting for row7Crow0 0x5b r/ w 0x00 gpi trigger mode 2 gpi edge-triggered detection setting for col7Ccol0
???????????????????????????????????????????????????????????????? maxim integrated products 10 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection keyscan controller key inputs are scanned statically, not dynamically, to ensure low-emi operation. since inputs only toggle in response to switch changes, the key matrix can be routed closer to sensitive circuit nodes. the keyscan controller debounces and maintains a fifo buffer of keypress and release events (including auto - repeated keypresses, if autorepeat is enabled). table 2 shows the key-switch order. the user-programmable key- switch debounce time and autosleep timer are derived from the 64khz clock, which in turn is derived from the 128khz oscillator. time delay for autorepeat and key- switch interrupt is based on the key-switch debounce time. there is no limitation for the number of keys pressed simultaneously as long as no ghost keys are generated. if the application requires fewer keys to be scanned, the unused key-switch ports can be configured as gpios. keys fifo register (0x00) the keys fifo register contains the information pertain - ing to the status of the keys fifo, as well as the key events that have been debounced. see table 7 . bits d[5:0] denote which of the 64 keys have been debounced and the keys are numbered as shown in table 2 . bit d7 indicates if there is more data in the fifo, except when d[5:0] indicate key 63 or key 62. when d[5:0] indi - cate key 63 or key 62, the host should read the fifo one more time to determine whether there is more data in the fifo. use key 62 and key 63 for rarely used keys. d6 indicates if it is a keypress or release event, except when d[5:0] indicate key 63 or key 62. reading the keyscan fifo clears the interrupt ( int ), depending on the setting of bit d5 in the configuration register (0x01). configuration register (0x01) the configuration register controls the i 2 c bus time - out feature, enables key-release detection, enables autowake, and determines how int is deasserted. write to bit d7 to put the device into sleep mode or operating mode. autosleep and autowake, when enabled, also change the status of d7. see table 8 . debounce register (0x02) the debounce register sets the keypress and key- release time for each debounce cycle. bits d[3:0] set the debounce time for keypresses, while bits d[7:4] set the debounce time for key releases. both debounce times are configured in increments of 2ms starting at 2ms and ending at 32ms. see table 9 . interrupt register (0x03) the interrupt register contains information related to the settings of the interrupt request function, as well as the sta - tus of the int output. if bits d[7:0] are set to 0x00, the int is disabled. there are two types of interrupts, the fifo- based interrupt and time-based interrupt. set bits d[4:0] to assert interrupts at the end of the selected number of debounce cycles following a key event. see table 10 . this number ranges from 1C31 debounce cycles. setting bits d[5:7] set the fifo-based interrupt when there are 2C14 key events stored in the fifo. both interrupts can be configured simultaneously and int asserts depending on which condition is met first. int deasserts depending on the status of bit d5 in the configuration register. autorepeat register (0x05) the device autorepeat feature notifies the host that at least one key has been pressed for a continuous period. the autorepeat register enables or disables this feature, sets the time delay after the last key event before the key- repeat code (0x7e) is entered into the fifo, and sets table 2. key-switch mapping pin col0 col1 col2 col3 col4 col5 col6 col7 row0 key 0 key 8 key 16 key 24 key 32 key 40 key 48 key 56 row1 key 1 key 9 key 17 key 25 key 33 key 41 key 49 key 57 row2 key 2 key 10 key 18 key 26 key 34 key 42 key 50 key 58 row3 key 3 key 11 key 19 key 27 key 35 key 43 key 51 key 59 row4 key 4 key 12 key 20 key 28 key 36 key 44 key 52 key 60 row5 key 5 key 13 key 21 key 29 key 37 key 45 key 53 key 61 row6 key 6 key 14 key 22 key 30 key 38 key 46 key 54 key 62 row7 key 7 key 15 key 23 key 31 key 39 key 47 key 55 key 63
???????????????????????????????????????????????????????????????? maxim integrated products 11 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection the frequency at which the key-repeat code is entered into the fifo thereafter. the key being pressed is not entered again into the fifo. bit d7 specifies whether the autorepeat function is enabled with 0, denoting autorepeat disabled, and 1, denoting autorepeat enabled. bits d[3:0] specify the autorepeat delay in terms of debounce cycles, ranging from eight debounce cycles to 128 debounce cycles. see table 11 . bits d[6:4] specify the autorepeat rate or frequency ranging from 4C32 debounce cycles. only one autorepeat code is entered into the fifo, regardless of the number of keys pressed. the autore - peat code continues to be entered in the fifo at the frequency set by bits d[3:0] until another key event is recorded. following the key-release event, if any keys are still pressed, the device restarts the autorepeat sequence. autosleep register (0x06) autosleep puts the device in sleep mode to draw minimal current. when enabled, the device enters sleep mode if no keys are pressed for the autoshutdown time. see table 12 . key-switch array size register (0x30) bits d[7:4] set the row size of the key-switch array, and bits d[3:0] set the column size of the key-switch array. see table 13 . set the bits to 0 if no key switches are used. the key-switch array should be connected begin - ning at row0 and col0. if not used as a key-switch matrix pin, then the pin can function as a gpio port. key-switch sleep mode in sleep mode, the device draws minimal current. switch- matrix current sources are turned off and pulled up to v cc . when autosleep is enabled, key-switch inactivity for a period longer than the autosleep time puts the part into sleep mode (fifo data is maintained). writing a 1 to d7 or a keypress can take the device out of sleep mode. bit d7 in the configuration register gives the sleep-mode status and can be read any time. autowake keypresses initiate autowake and the device goes into operating mode. keypresses that autowake the device are not lost. when a key is pressed while the device is in sleep mode, all analog circuitry, including switch-matrix current sources, turn on in 2ms. the initial key needs to be pressed for 2ms plus the debounce time to be stored in the fifo. write a 0 to bit d1 in the configuration regis - ter (0x01) to disable autowake. fifo overflow the fifo overflow status occurs when the fifo is full (16 bytes) and additional events occur. if key release is disabled, then the fifo overflow status occurs when the fifo is full and not upon additional key events. when the fifo is overflowed, the first byte read from the fifo buffer is the overflow byte (0x7f). the order of the original 16 bytes of event data is preserved, but further events could be lost. when the fifo is full, if the 18th key event is a key release, then the fifo overflow status is removed. gpios the device has 16 gpio ports, four of which have led control functions. the ports can be used as logic inputs or logic outputs. col7Ccol4 are also configurable as constant-current pwm led drivers. each ports logic level is referenced to v cc or v la . the gpio ports inputs can also be debounced. when in pwm mode, the ports are set up to start their pwm cycle in 45 n phase incre - ments. this prevents large current spikes on the led supply voltage when driving multiple leds. led driver enable register (0x31) bits d[3:0] correspond to col7Ccol4 on the device. set the corresponding bit to 1 for enabling the led driver circuitry and 0 for normal gpio function. see table 14 . gpio direction 1 and 2 registers (0x34, 0x35) these registers configure the pins as an input or an output port. gpio direction 1 register bits d[7:0] correspond with row7Crow0. see table 15 . gpio direction 2 register bits d[7:0] correspond with col7Ccol0. see table 16 . set the corresponding bit to 0 to configure as input and 1 to configure as output. when the port is initially programmed as an input, there is a delay of one debounce period prior to detecting a transition on the input port. this is to prevent a false interrupt from occurring when changing a port from an output to an input.
???????????????????????????????????????????????????????????????? maxim integrated products 12 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection gpo output mode 1 and 2 registers (0x36, 0x37) these registers configure the pin as an open-drain or push-pull output. gpo output mode 1 register bits d[7:0] correspond with row7Crow0. see table 17 . gpo output mode 2 register bits d[7:0] correspond with col7Ccol0. see table 18 . set the corresponding bit to 0 to configure the output mode as open-drain and 1 to configure the output mode as push-pull. gpio supply voltage 1 and 2 registers (0x38, 0x39) these registers configure input and output voltages to be referenced to v cc or v la . gpio supply voltage 1 register bits d[7:0] correspond with row7Crow0. see table 19 . gpio supply voltage 2 register bits d[7:0] cor - respond with col7Ccol0. see table 20 . set the bit to 0 for input/output voltages referenced to v cc or set the bit to 1 for the input/output voltage referenced to v la . gpio values 1 and 2 registers (0x3a, 0x3b) the gpio values 1 and 2 registers contain the debounced input data for all the gpios for row7Crow0 and col7C col0, respectively. see tables 21 and 22 . there is one debounce period delay prior to detecting a transition on the input port. this prevents a false interrupt from occur - ring when changing a port from an output to an input. the gpio values 1 and 2 registers report the state of all input ports regardless of any interrupt mask settings. when writing to the gpio values 1 and 2 registers, the corresponding port voltage is set high when written 1 or cleared when written 0. reading the port when config - ured as an output always returns the value 0 for the cor - responding port regardless of the output value. gpio level-shifter enable register (0x3c) enabling bit d_ in this register enables the direct level shifter between gpio pins col_ and row_. see table 23 . as an example, setting d5 to logic-high enables level shifting between col5 and row5. the direction of the level shifter is controlled by the gpio direction 2 register (0x35). when setting the correspond - ing bit in the gpio direction 2 register to 0, col_ are inputs, and row_ are outputs. when setting the bit to 1, row_ become inputs and col_ become outputs. gpio global configuration register (0x40) the gpio global configuration register controls the main settings for the gpio ports. see table 24 . bit d5 enables interrupt generation for i 2 c timeouts. d4 is the main enable/shutdown bit for the gpios. bit d3 functions as a software reset for the gpio registers (0x31 to 0x5b). bits d[2:0] set the fade-in/out time for the led drivers. gpio debounce configuration register (0x42) the gpio debounce configuration register sets the amount of time a gpio must be held in order for the device to register a logic transition. see table 25 . the gpio debounce setting is independent of the key-switch debounce setting. five bits (d[4:0]) set 32 possible debounce times from 9ms up to 40ms. led constant-current setting register (0x43) the led constant-current setting register sets the global constant-current amount. see table 26 . bit d0 selects the global current values between 10ma and 20ma. this setting only applies to the led driver-enabled pins, col7Ccol4. common pwm ratio register (0x45) the common pwm ratio register stores the common constant-current output pwm duty cycle. see table 27 . the values stored in this register translate over to a pwm ratio in the same manner as the individual pwm ratio reg - isters (0x50 to 0x53). ports can use their own individual pwm value or the common pwm value. write to this reg - ister to change the pwm ratio of several ports at once. i 2 c timeout flag register (0x48) (read only) the i 2 c timeout flag register contains a single bit (d0) that indicates if an i 2 c timeout has occurred. see table 28 . read this register to clear an i 2 c timeout- initiated interrupt. col4Ccol7 individual pwm ratio registers (0x50 to 0x53) each led driver port has an individual pwm ratio register, 0x50 to 0x53. see table 29 . use values 0x00 to 0xfe in these registers to configure the number of cycles out of 256 the output sinks current (led is on), from 0 cycles to 254 cycles. use 0xff to have an output continuously sink current (always on). for applications requiring multiple ports to have the same intensity, program a particular ports configuration register (0x54 to 0x57) to use the common pwm ratio register (0x45). new pwm settings take place at the beginning of a pwm cycle, to allow changes from common intensity to individual intensity with no interruption in the pwm cycle.
???????????????????????????????????????????????????????????????? maxim integrated products 13 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection col4Ccol7 led configuration registers (0x54 to 0x57) registers 0x54 to 0x57 set individual configurations for each port. see table 30 . d5 sets the ports pwm setting to either the common or individual pwm setting. bits d[4:2] enable and set the ports individual blink period from 0 to 4096ms. bits d[1:0] set a ports blink duty cycle. interrupt mask 1 and 2 registers (0x58, 0x59) the interrupt mask 1 and 2 registers control which ports trigger an interrupt for row7Crow0 and col7Ccol0, respectively. see tables 31 and 32 . set the bit to 0 to enable the interrupt. set the bit to 1 to mask the interrupt. if the port that has generated the interrupt is not masked, the interrupt causes the int signal to assert. a read of the gpio values 1 and 2 registers (0x3a, 0x3b) is required to deassert the int pin. note that transitions that occur while the int signal is asserted, but before the read of the gpio values 1 and 2 registers, set the appropriate bit of the gpio values 1 and 2 registers only, but has no effect on the int pin as it is already asserted. however, transi - tions that occur when the i 2 c is active cannot be latched into the gpio values 1 and 2 registers until after the read has taken place. if there are transitions that cause the int signal to assert, during the time of an i 2 c read, they cause the int signal to reassert once the read transac - tion has taken place. note that the interrupt configura - tions only apply when a port is configured as an input. gpi trigger mode 1 and 2 registers (0x5a, 0x5b) the gpi trigger mode 1 and 2 registers control how ports can trigger an interrupt for row7Crow0 and col7C col0, respectively. see tables 33 and 34 . set the bit to 0 for rising-edge triggering. set the bit to 1 for rising- and falling-edge triggering. the inputs are debounced (if enabled) by taking a snap - shot of the port state when the transition occurs, and another after the debounce time has elapsedensuring that the state of the port is stable prior to triggering the interrupt. after the debounce cycle, an interrupt is gener - ated and the int pin asserted if it is not masked for that particular port. regardless of whether or not the int sig - nal is masked, the gpio values 1 and 2 registers (0x3a, 0x3b) report the state of all input ports. sleep mode the device is put into sleep mode by clearing bit d7 in the configuration register, or after power-on reset (por). in sleep mode, the keyscan controller is disabled and the device draws minimal current. no additional supply cur - rent is drawn if no keys are pressed. all switch-matrix cur - rent sources are turned off, and row outputs row7Crow0 are low and column outputs col7Ccol0 become high. the device is taken out of sleep mode and put into oper - ating mode by setting bit d7 in the configuration register. the keyscan controller fifo buffers are cleared and key monitoring starts. note that rewriting the configuration register with bit d7 high, when bit d7 was already high, does not clear the fifos. the fifos are only cleared when the device is changing state from sleep mode to operating mode. in sleep mode, the internal oscillator is disabled and i 2 c timeout features are disabled. the gpo or led ports consume current even in sleep mode. the part does not enter sleep mode if any of the gpios or led drivers are enabled. led fade set the fade cycle time in the gpio global configuration register (0x40) to a non-zero value to enable fade in/out. see table 24 . fade in increases an leds pwm intensity in 16 even steps, from zero to its stored value. fade out decreases an leds pwm intensity in 16 even steps from its current value to zero. fading occurs automatically in any of the following scenarios: ? change the common pwm register value from any value to zero to cause all ports using the common pwm register settings to fade out. no ports using individual pwm settings are affected. ? change the common pwm register value to any value from zero to cause all ports using the common pwm register settings to fade in. no ports using individual pwm settings are affected. ? take the part out of sleep mode to cause all ports to fade in. changing an individual pwm intensity dur - ing fade in automatically cancels that ports fade and immediately outputs at its newly programmed intensity.
???????????????????????????????????????????????????????????????? maxim integrated products 14 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection ? put the part into sleep mode to cause all ports to fade out. changing an individual pwm intensity during fade out automatically cancels that ports fade and immediately turns off. led pwm each port has an individual pwm ratio register. the value stored in this register configures the number of cycles out of 255 that the output is sinking current (led is on). setting a value of 0xff in an individual intensity register sets the output to continuously sink current (always on). conversely, setting a value of 0x00 in an individual inten - sity register sets the output in a high-impedance state (always off). for applications requiring multiple ports to have the same intensity, the common pwm ratio intensity setting can be used in lieu of the individual intensity setting. to use the common intensity setting, program bit d5 of the corresponding ports configuration register to logic-high. setting a port to use the common pwm ratio setting copies the value of the common intensity register into the individual intensity register at the beginning of each pwm cycle. this allows an output port to be seamlessly changed from common intensity to individual intensity with no interruption in the pwm cycle. outputs are configured to sink a constant current of either 10ma or 20ma during the period of time when the output is on. the setting in the individual gpio constant-current setting register (0x43) controls the value of the current. led blink each led driver-supported port has its own blink-control settings through registers 0x54 to 0x57. see table 30 . the blink period ranges from 0 (blink disabled) to 4.096s. settable blink duty cycles range from 6.25% to 50%. all blink periods start at the same pwm cycle for synchro - nized blinking between multiple ports. each port has its own counter to generate blink timing. the blink counter can be programmed to cause the out - put to gate off and on at a programmable rate. the blink period can be set to 256ms, 512ms, 1.024s, 2.048s, or 4.096s using d[4:2] of the ports individual configuration register. the percentage of time that the led is on for one blink cycle is set to 50%, 25%, 12.5%, or 6.25% by d[1:0] of the individual configuration register. interrupts three possible sources generate int : key-switch fifo level/debounce cycle settings, i 2 c timeout, or gpios configured as inputs (registers 0x03, 0x48, 0x5a, and 0x5b). read the respective data/status registers for each type of interrupt to clear int . if multiple sources generate the interrupt, all the related status registers must be read to clear int . serial interface figure 1 shows the two-wire serial interface timing details. figure 1. two-wire serial interface timing details sda scl t hd, sta t low t high t r t f t su, dat t su, sta t su, sto t buf t hd, sta t hd, dat start condition stop condition start condition repeated start condition t f t f, tx t r
???????????????????????????????????????????????????????????????? maxim integrated products 15 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection figure 2. start and stop conditions serial addressing the device operates as a slave that sends and receives data through an i 2 c-compatible two-wire interface. the interface uses a serial-data line (sda) and a serial- clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a master (typically a microcontroller) initiates all data transfers to and from the device and generates the scl clock that synchronizes the data transfer. the devices sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k, is required on sda. the devices scl line operates only as an input. a pullup resistor is required on scl if there are multiple masters on the two-wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start (s) condition ( figure 2 ) sent by a master, followed by the devices 7-bit slave address plus r/ w bit, a register address byte, one or more data bytes, and finally, a stop (p) condition. start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse ( figure 3 ). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit ( figure 4 ), which the recipient uses to handshake receipt of each byte of data. thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse; therefore, the sda line is stable low during the high period of the clock pulse. when the master is trans - mitting to the device, the device generates the acknowl - edge bit because the device is the recipient. when the device is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. figure 3. bit transfer sda scl start condition stop condition s p sda scl data line stable; data valid change of data allowed
???????????????????????????????????????????????????????????????? maxim integrated products 16 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection slave addresses the device has two 7-bit long slave addresses. the bit following a 7-bit slave address is the r/ w bit, which is low for a write command and high for a read command. the first 4 bits (msbs) of the device slave addresses are always 0111. slave address bits a[3:1] correspond, by the matrix in table 3 , to the states of the device address input pin ad0, and a0 corresponds to the r/ w bit ( figure 5 ). the ad0 input can be connected to any of four signals: gnd, v cc , sda, or scl, giv - ing four possible slave-address pairs, allowing up to four devices to share the same bus. because sda and scl are dynamic signals, care must be taken to ensure that ad0 transitions no sooner than the signals on sda and scl. the device monitors the bus continuously, waiting for a start condition, followed by its slave address. when the device recognizes its slave address, it acknowledges and is then ready for continued communication. bus timeout the device features a 20ms (min) bus timeout on the two-wire serial interface, largely to prevent the device from holding the sda i/o low during a read transac - tion should the scl lock up for any reason before a serial transaction is completed. bus timeout operates by causing the device to internally terminate a serial trans - action, either read or write, if the time between adjacent edges on scl exceeds 20ms. after a bus timeout, the device waits for a valid start condition before respond - ing to a consecutive transmission. this feature can be enabled or disabled under user control by writing to the configuration register. message format for writing the keyscan controller a write to the device comprises the transmission of the slave address with the r/ w bit set to zero, followed by at least one byte of information. the first byte of information is the com - mand byte. the command byte determines which register of the device is to be written by the next byte, if received. if a stop condition is detected after the command byte is received, the device takes no further action ( figure 6 ) beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the device selected by the command byte ( figure 7 ). if multiple data bytes are transmitted before a stop condi - tion is detected, these bytes are generally stored in sub - sequent internal registers of the device, because the com - mand-byte address generally autoincrements ( table 4 ). figure 4. acknowledge figure 5. slave address table 3. two-wire interface address map ad0 pin device address a7 a6 a5 a4 a3 a2 a1 a0 gnd 0 1 1 1 0 0 0 r/ w v cc 0 1 sda 1 0 scl 1 1 scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s sda scl 0 1 1 a 3 a 2 a 1 1 msb lsb ack r/w
???????????????????????????????????????????????????????????????? maxim integrated products 17 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection message format for reading the keyscan controller the device is read using the internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. the pointer generally autoincrements after each data byte is read using the same rules as for a write ( table 4 ). thus, a read is initiated by first configuring the devices command byte by performing a write ( figure 6 ). the master can now read n consecutive bytes from the device, with the first data byte being read from the reg - ister addressed by the initialized command byte. when performing read-after-write verification, remember to reset the command bytes address because the stored command byte address is generally autoincremented after the write ( figure 8 , table 4 ). figure 7. command and single data byte received figure 6. command byte received figure 8. n data bytes received table 4. autoincrement rules register function address code (hex) autoincrement address (hex) keys fifo 0x00 0x00 autosleep 0x06 0x00 all other key switches 0x01 to 0x05 addr + 0x01 all other gpios 0x30 to 0x5b addr + 0x01 s a a p 0 slave address command byte d7 d6 d5 d4 d3 d2 d1 d0 command byte is stored on receipt of acknowledge condition acknowledge from max7370 acknowledge from max7370 r/w s a a a p 0 slave address command byte data byte 1 byte autoincrement command byte address d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max7370 acknowledge from max7370 acknowledge from max7370 r/w s a a a p 0 slave address command byte data byte n bytes autoincrement command byte address d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max7370 acknowledge from max7370 acknowledge from max7370 r/w
???????????????????????????????????????????????????????????????? maxim integrated products 18 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection operation with multiple masters when the device is operated on a two-wire interface with multiple masters, a master reading the device uses a repeated start between the write that sets the devices address pointer, and the read(s) that takes the data from the location(s). this is because it is possible for master 2 to take over the bus after master 1 has set up the devices address pointer but before master 1 has read the data. if master 2 subsequently resets the devices address pointer, master 1s read can be from an unexpected location. command address autoincrementing address autoincrementing allows the device to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. the command address stored in the device gener - ally increments after each data byte is written or read ( table 4 ). autoincrement only functions when doing a multiburst read or write. applications information reset from i 2 c after a catastrophic event such as esd discharge or microcontroller reset, use bit d7 of the configuration reg - ister (0x01) as a software reset for the key switches. use bit d4 of the gpio global configuration register (0x40) as a software reset for the gpios. ghost-key elimination ghost keys are a phenomenon inherent with key-switch matrices. when three switches located at the corners of a matrix rectangle are pressed simultaneously, the switch that is located at the last corner of the rectangle (the ghost key) also appears to be pressed. this occurs because the potentials at the two sides of the ghost-key switch are identical due to the other three connections the switch is electrically shorted by the combination of the other three switches ( figure 9 ). because the key appears to be pressed electrically, it is impossible to detect which of the four keys is the ghost key. the device employs a proprietary scheme that detects any three-key combination that generates a fourth ghost key, and does not report the third key that causes a ghost-key event. this means that although ghost keys are never reported, many combinations of three keys are effectively ignored when pressed at the same time. applications requiring three-key combinations (such as ) must ensure that the three keys are not wired in positions that define the vertices of a rect - angle ( figure 10 ). there is no limit on the number of keys that can be pressed simultaneously as long as the keys do not generate ghost-key events and the fifo is not full. low-emi operation the device uses two techniques to minimize emi radiat - ing from the key-switch wiring. first, the voltage across the switch matrix never exceeds 0.5v if not in sleep mode, independent of supply voltage v cc . this reduces the voltage swing at any node when a switch is pressed to 0.5v (max). second, the keys are not dynamically scanned, which would cause the key-switch wiring to continuously radiate interference. instead, the keys are monitored for current draw (only occurs when pressed), and debounce circuitry only operates when one or more keys are actually pressed. figure 9. ghost-key phenomenon figure 10. valid three-key combinations regular keypress event ghost-key event key-switch matrix key-switch matrix key-switch matrix examples of valid three-key combinations
???????????????????????????????????????????????????????????????? maxim integrated products 19 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection switch on-resistance the device is designed to be insensitive to resistance, either in the key switches, or the switch routing to and from the appropriate col_ and row_ up to 5k i (max). these controllers are therefore compatible with low-cost membrane and conductive carbon switches. hot insertion the int , scl, and ad0 inputs and sda remain high impedance with up to 5.5v asserted on them when the device powers down (v cc = 0v). i/o ports remain high impedance with up to 5.5v asserted on them when not powered. use the device in hot-swap applications. staggered pwm the leds on-time in each pwm cycle is phase delayed by 45 n into four evenly spaced start positions. optimize phas - ing, when using fewer than four ports as constant-current outputs, by allocating the ports with the most appropriate start positions. for example, if using two constant-current outputs, choose col4 and col6 because their pwm start positions are evenly spaced. in general, choose the ports that spread the current demand from the ports load supply. power-supply considerations the device operates with a 1.62v to 3.6v power-supply voltage. bypass the power supply (v cc ) to gnd with a 0.1f or higher ceramic capacitor as close as possible to the device. bypass the logic power supply (v la ) to gnd with a 0.1f or higher ceramic capacitor as close as possible to the device. esd protection all the device pins meet the 1.5kv human body model esd tolerances. key-switch inputs and gpios meet iec 61000-4-2 esd protection. the iec test stresses consist of 10 consecutive esd discharges per polarity at the maximum specified level and below (per iec 61000-4-2). test criteria include: ? the powered device does not latch up during the esd discharge event. ? the device subsequently passes the final test used for prescreening. tables 5 and 6 are taken from the iec 61000-4-2: edition 1.1 1999-05: electromagnetic compatibility (emc) testing and measurement techniqueselectrostatic dis - charge immunity test . table 5. esd test levels table 6. esd waveform parameters x = open level. the level has to be specified in the dedicated equipment specification. if higher voltages than those shown are specified, special test equipment might be needed. 1acontact discharge 1bair discharge level test voltage (kv) level test voltage (kv) 1 2 1 2 2 4 2 4 3 6 3 8 4 8 4 15 x special x special level indicated voltage (kv) first peak of current discharge q 10% (a) rise time (t r ) with discharge switch (ns) current ( q 30%) at 30ns (a) current ( q 30%) at 60ns (a) 1 2 7.5 0.7 to 1 4 2 2 4 15 0.7 to 1 8 4 3 6 22.5 0.7 to 1 12 6 4 8 30 0.7 to 1 16 8
???????????????????????????????????????????????????????????????? maxim integrated products 20 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 7. keys fifo register format (0x00) register tables special function keys fifo register data d7 d6 d5 d4 d3 d2 d1 d0 the key number indicated by d[5:0] is a key event. d7 is always for a keypress of key 62 and key 63. when d7 is 0, the key read is the last data in the fifo. when d7 is 1, there is more data in the fifo. when d6 is 1, key data read from the fifo is a key release. when d6 is 0, key data read from the fifo is a keypress. fifo not- empty flag key- release flag key number/key event fifo is empty. 0 0 1 1 1 1 1 1 fifo is overflow. continue to read data in the fifo. 0 1 1 1 1 1 1 1 key 63 is pressed. read one more time to determine whether there is more data in the fifo. 1 0 1 1 1 1 1 1 key 63 is released. read one more time to determine whether there is more data in the fifo. 1 1 1 1 1 1 1 1 key repeat. indicates the last data in the fifo. 0 0 1 1 1 1 1 0 key repeat. indicates more data in the fifo. 0 1 1 1 1 1 1 0 key 62 is pressed. read one more time to determine whether there is more data in the fifo. 1 0 1 1 1 1 1 0 key 62 is released. read one more time to determine whether there is more data in the fifo. 1 1 1 1 1 1 1 0
???????????????????????????????????????????????????????????????? maxim integrated products 21 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 8. configuration register (0x01) x = dont care. register bit description value function default value d7 sleep x (when 0x40 d4 = 1) key-switch operating mode. key switches always remain active when constant-current pwm is enabled (bit 4 of register 0x40 is high), regardless of autosleep, autowake, or an i 2 c write to this bit. 0 0 (when 0x40 d4 = 0) key-switch sleep mode. the entire chip is shut down. when constant-current pwm is disabled (bit 4 of register 0x40 is low), i 2 c write, autosleep, and autowake all can change this bit. this bit can be read back by i 2 c any time for current status. 1 (when 0x40 d4 = 0) key-switch operating mode. d6 reserved 0 0 d5 interrupt 0 int cleared when the fifo is empty. 0 1 int cleared after host read. in this mode, i 2 c should read the fifo until interrupt condition is removed or further int could be lost. d4 reserved 0 0 d3 key-release enable 0 disable key releases. 1 1 enable key releases. d2 reserved 0 0 d1 autowake enable 0 disable keypress wakeup. 1 1 enable keypress wakeup. d0 timeout disable 0 i 2 c timeout enabled. 1 1 i 2 c timeout disabled.
???????????????????????????????????????????????????????????????? maxim integrated products 22 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 9. key-switch debounce register (0x02) table 10. key-switch interrupt register (0x03) x = dont care. x = dont care. register description register data d7 d6 d5 d4 d3 d2 d1 d0 debounce time release debounce time press debounce time 2ms x 0 0 0 0 4ms 0 0 0 1 6ms 0 0 1 0 ? 28ms x 1 1 0 1 30ms 1 1 1 0 32ms 1 1 1 1 2ms 0 0 0 0 x 4ms 0 0 0 1 6ms 0 0 1 0 ? 28ms 1 1 0 1 x 30ms 1 1 1 0 32ms 1 1 1 1 power-on default (32ms) 1 1 1 1 1 1 1 1 register description register data d7 d6 d5 d4 d3 d2 d1 d0 fifo-based int time-based int power-up default setting all int disabled 0 0 0 0 0 0 0 0 time-based int disabled x 0 0 0 0 0 int asserts every debounce cycle 0 0 0 0 1 int asserts every 2 debounce cycles 0 0 0 1 0 ? int asserts every 29 debounce cycles x 1 1 1 0 1 int asserts every 30 debounce cycles 1 1 1 1 0 int asserts every 31 debounce cycles 1 1 1 1 1 fifo-based int disabled 0 0 0 x int asserts when the fifo has 2 key events 0 0 1 int asserts when the fifo has 4 key events 0 1 0 ? int asserts when the fifo has 10 key events 1 0 1 x int asserts when the fifo has 12 key events 1 1 0 int asserts when the fifo has 14 key events 1 1 1 both time-based and fifo-based interrupts active not all zero not all zero
???????????????????????????????????????????????????????????????? maxim integrated products 23 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 11. key-switch autorepeat register (0x05) table 12. autosleep register (0x06) x = dont care. register description register data d7 d6 d5 d4 d3 d2 d1 d0 enable autorepeat rate autorepeat delay autorepeat is disabled 0 x x x x x x x autorepeat is enabled 1 autorepeat rate autorepeat delay autorepeat delay is 8 debounce cycles 1 x 0 0 0 0 autorepeat delay is 16 debounce cycles 1 0 0 0 1 autorepeat delay is 24 debounce cycles 1 0 0 1 0 ? autorepeat delay is 112 debounce cycles 1 x 1 1 0 1 autorepeat delay is 120 debounce cycles 1 1 1 1 0 autorepeat delay is 128 debounce cycles 1 1 1 1 1 autorepeat frequency is 4 debounce cycles 1 0 0 0 x autorepeat frequency is 8 debounce cycles 1 0 0 1 autorepeat frequency is 12 debounce cycles 1 0 1 0 ? autorepeat frequency is 24 debounce cycles 1 1 0 1 x autorepeat frequency is 28 debounce cycles 1 1 1 0 autorepeat frequency is 32 debounce cycles 1 1 1 1 power-on default setting 0 0 0 0 0 0 0 0 register description autosleep (ms) register data reserved autoshutdown time d7 d6 d5 d4 d3 d2 d1 d0 autosleep disabled 0 0 0 0 0 0 0 0 8192 0 0 0 0 0 0 0 1 4096 0 0 0 0 0 0 1 0 2048 0 0 0 0 0 0 1 1 1024 0 0 0 0 0 1 0 0 512 0 0 0 0 0 1 0 1 256 0 0 0 0 0 1 1 0 256 0 0 0 0 0 1 1 1 power-up default settings 0 0 0 0 0 1 1 1
???????????????????????????????????????????????????????????????? maxim integrated products 24 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 13. key-switch array size register (0x30) table 14. led driver enable register (0x31) x = dont care. register description register data d7 d6 d5 d4 d3 d2 d1 d0 rows columns no rows are key switches 0 0 0 0 x row0 is a key switch 0 0 0 1 row0 to row1 are key switches 0 0 1 0 row0 to row2 are key switches 0 0 1 1 row0 to row3 are key switches 0 1 0 0 row0 to row4 are key switches 0 1 0 1 row0 to row5 are key switches 0 1 1 0 row0 to row6 are key switches 0 1 1 1 row0 to row7 are key switches 1 x x x no columns are key switches x 0 0 0 0 col0 is a key switch 0 0 0 1 col0 to col1 are key switches 0 0 1 0 col0 to col2 are key switches 0 0 1 1 col0 to col3 are key switches 0 1 0 0 col0 to col4 are key switches 0 1 0 1 col0 to col5 are key switches 0 1 1 0 col0 to col6 are key switches 0 1 1 1 col0 to col7 are key switches 1 x x x power-up default setting 1 1 1 1 1 1 1 1 register bit description value function default value d[7:4] reserved 0000 0000 d3 col7 0 gpio function 0 1 led driver enable d2 col6 0 gpio function 0 1 led driver enable d1 col5 0 gpio function 0 1 led driver enable d0 col4 0 gpio function 0 1 led driver enable
???????????????????????????????????????????????????????????????? maxim integrated products 25 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 15. gpio direction 1 register (0x34) table 16. gpio direction 2 register (0x35) register bit description value function default value d7 row7 0 set as input pin 0 1 set as output pin d6 row6 0 set as input pin 0 1 set as output pin d5 row5 0 set as input pin 0 1 set as output pin d4 row4 0 set as input pin 0 1 set as output pin d3 row3 0 set as input pin 0 1 set as output pin d2 row2 0 set as input pin 0 1 set as output pin d1 row1 0 set as input pin 0 1 set as output pin d0 row0 0 set as input pin 0 1 set as output pin register bit description value function default value d7 col7 0 set as input pin 0 1 set as output pin d6 col6 0 set as input pin 0 1 set as output pin d5 col5 0 set as input pin 0 1 set as output pin d4 col4 0 set as input pin 0 1 set as output pin d3 col3 0 set as input pin 0 1 set as output pin d2 col2 0 set as input pin 0 1 set as output pin d1 col1 0 set as input pin 0 1 set as output pin d0 col0 0 set as input pin 0 1 set as output pin
???????????????????????????????????????????????????????????????? maxim integrated products 26 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 17. gpo output mode 1 register (0x36) table 18. gpo output mode 2 register (0x37) note: when programmed as gpo, col7Ccol4 are always open drain and bits d[7:4] are not writable. register bit description value function default value d7 row7 0 port is an open-drain output 1 1 port is a push-pull output d6 row6 0 port is an open-drain output 1 1 port is a push-pull output d5 row5 0 port is an open-drain output 1 1 port is a push-pull output d4 row4 0 port is an open-drain output 1 1 port is a push-pull output d3 row3 0 port is an open-drain output 1 1 port is a push-pull output d2 row2 0 port is an open-drain output 1 1 port is a push-pull output d1 row1 0 port is an open-drain output 1 1 port is a push-pull output d0 row0 0 port is an open-drain output 1 1 port is a push-pull output register bit description value function default value d7 col7 0 port is an open-drain output 0 d6 col6 0 port is an open-drain output 0 d5 col5 0 port is an open-drain output 0 d4 col4 0 port is an open-drain output 0 d3 col3 0 port is an open-drain output 1 1 port is a push-pull output d2 col2 0 port is an open-drain output 1 1 port is a push-pull output d1 col1 0 port is an open-drain output 1 1 port is a push-pull output d0 col0 0 port is an open-drain output 1 1 port is a push-pull output
???????????????????????????????????????????????????????????????? maxim integrated products 27 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 19. gpio supply voltage 1 register (0x38) table 20. gpio supply voltage 2 register (0x39) register bit description value function default value d7 row7 0 row7 supplied by v cc 0 1 row7 supplied by v la d6 row6 0 row6 supplied by v cc 0 1 row6 supplied by v la d5 row5 0 row5 supplied by v cc 0 1 row5 supplied by v la d4 row4 0 row4 supplied by v cc 0 1 row4 supplied by v la d3 row3 0 row3 supplied by v cc 0 1 row3 supplied by v la d2 row2 0 row2 supplied by v cc 0 1 row2 supplied by v la d1 row1 0 row1 supplied by v cc 0 1 row1 supplied by v la d0 row0 0 row0 supplied by v cc 0 1 row0 supplied by v la register bit description value function default value d7 col7 0 col7 supplied by v cc 0 1 col7 supplied by v la d6 col6 0 col6 supplied by v cc 0 1 col6 supplied by v la d5 col5 0 col5 supplied by v cc 0 1 col5 supplied by v la d4 col4 0 col4 supplied by v cc 0 1 col4 supplied by v la d3 col3 0 col3 supplied by v cc 0 1 col3 supplied by v la d2 col2 0 col2 supplied by v cc 0 1 col2 supplied by v la d1 col1 0 col1 supplied by v cc 0 1 col1 supplied by v la d0 col0 0 col0 supplied by v cc 0 1 col0 supplied by v la
???????????????????????????????????????????????????????????????? maxim integrated products 28 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 21. gpio values 1 register (0x3a) table 22. gpio values 2 register (0x3b) * open-drain output, pullup resistor required. register bit description value function default value d7 row7 0 clear row7 low 1 1 set row7 high d6 row6 0 clear row6 low 1 1 set row6 high d5 row5 0 clear row5 low 1 1 set row5 high d4 row4 0 clear row4 low 1 1 set row4 high d3 row3 0 clear row3 low 1 1 set row3 high d2 row2 0 clear row2 low 1 1 set row2 high d1 row1 0 clear row1 low 1 1 set row1 high d0 row0 0 clear row0 low 1 1 set row0 high register bit description value function default value d7 col7 0 clear col7 low 1 1 set col7 high* d6 col6 0 clear col6 low 1 1 set col6 high* d5 col5 0 clear col5 low 1 1 set col5 high* d4 col4 0 clear col4 low 1 1 set col4 high* d3 col3 0 clear col3 low 1 1 set col3 high d2 col2 0 clear col2 low 1 1 set col2 high d1 col1 0 clear col1 low 1 1 set col1 high d0 col0 0 clear col0 low 1 1 set col0 high
???????????????????????????????????????????????????????????????? maxim integrated products 29 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 23. gpio level-shifter enable register (0x3c) register bit description value function default value d7 col7 0 level shifting disabled 0 1 level shift between col7 and row7 enabled; direction controlled by gpio direction 2 register (0x35) d6 col6 0 level shifting disabled 0 level shift between col6 and row6 enabled; direction controlled by gpio direction 2 register (0x35) d5 col5 0 level shifting disabled 0 1 level shift between col5 and row5 enabled; direction controlled by gpio direction 2 register (0x35) d4 col4 0 level shifting disabled 0 1 level shift between col4 and row4 enabled; direction controlled by gpio direction 2 register (0x35) d3 col3 0 level shifting disabled 0 1 level shift between col3 and row3 enabled; direction controlled by gpio direction 2 register (0x35) d2 col2 0 level shifting disabled 0 1 level shift between col2 and row2 enabled; direction controlled by gpio direction 2 register (0x35) d1 col1 0 level shifting disabled 0 1 level shift between col1 and row1 enabled; direction controlled by gpio direction 2 register (0x35) d0 col0 0 level shifting disabled 0 1 level shift between col0 and row0 enabled; direction controlled by gpio direction 2 register (0x35)
???????????????????????????????????????????????????????????????? maxim integrated products 30 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 24. gpio global configuration register (0x40) table 25. gpio debounce configuration register (0x42) register description register data d7 d6 d5 d4 d3 d2 d1 d0 reserved debounce time power-up default setting debounce time is 9ms 0 0 0 0 0 0 0 0 debounce time is 10ms 0 0 0 0 0 0 0 1 debounce time is 11ms 0 0 0 0 0 0 1 0 debounce time is 12ms 0 0 0 0 0 0 1 1 ? debounce time is 37ms 0 0 0 1 1 1 0 0 debounce time is 38ms 0 0 0 1 1 1 0 1 debounce time is 39ms 0 0 0 1 1 1 1 0 debounce time is 40ms 0 0 0 1 1 1 1 1 register bit description value function default value d[7:6] reserved 0 00 d5 i 2 c timeout interrupt enable 0 disabled 0 1 int is asserted when i 2 c bus times out. int is deasserted when a read is performed on the i 2 c timeout flag register (0x48). d4 gpio enable 0 pwm, constant-current circuits, and gpis are shut down. gpo values depend on their setting. register 0x31 to 0x5b values are stored and cannot be changed. the entire part is shut down if the key switches are in sleep mode (d7 of register 0x01). 0 1 normal gpio operation. pwm, constant-current circuits, and gpios are enabled regardless of key-switch sleep-mode state (see table 8). d3 gpio reset 0 normal operation 0 1 return all gpio registers (registers 0x31 to 0x5b) to their por value. this bit is momentary and resets itself to 0 after the write cycle. d[2:0] fade-in/out time 000 no fading 000 xxx pwm intensity ramps up (down) between the common pwm value and 0% duty cycle in 16 steps over the following time period: d[2:0] = 001 = 256ms d[2:0] = 010 = 512ms d[2:0] = 011 = 1024ms d[2:0] = 100 = 2048ms d[2:0] = 101 = 4096ms d[2:0] = 110/111 = undefined
???????????????????????????????????????????????????????????????? maxim integrated products 31 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 26. led constant-current setting register (0x43) table 27. common pwm register (0x45) table 28. i 2 c timeout flag register (0x48) (read only) register bit description value function default value d[7:6] reserved 11 set always as 11 11 d[5:1] reserved 00000 00000 d0 constant-current setting 0 constant current is 20ma 0 1 constant current is 10ma register description register data d7 d6 d5 d4 d3 d2 d1 d0 common pwm power-up default setting common pwm ratio is 0/256 0 0 0 0 0 0 0 0 common pwm ratio is 1/256 0 0 0 0 0 0 0 1 common pwm ratio is 2/256 0 0 0 0 0 0 1 0 common pwm ratio is 3/256 0 0 0 0 0 0 1 1 ? common pwm ratio is 252/256 1 1 1 1 1 1 0 0 common pwm ratio is 253/256 1 1 1 1 1 1 0 1 common pwm ratio is 254/256 1 1 1 1 1 1 1 0 common pwm ratio is 256/256 (100% duty cycle) 1 1 1 1 1 1 1 1 register bit description value function default value d[7:1] reserved 0000000 0000000 d0 i 2 c timeout flag 0 no i 2 c timeout has occurred since last read or por. 0 1 i 2 c timeout has occurred since last read or por. this bit is reset to zero when a read is performed on this register. i 2 c timeouts must be enabled for this function to work (see table 8).
???????????????????????????????????????????????????????????????? maxim integrated products 32 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 29. col4Ccol7 individual pwm ratio registers (0x50 to 0x53) table 30. col4Ccol7 led configuration registers (0x54 to 0x57) register description register data d7 d6 d5 d4 d3 d2 d1 d0 port pwm power-up default setting port pwm ratio is 0/256 0 0 0 0 0 0 0 0 port pwm ratio is 1/256 0 0 0 0 0 0 0 1 port pwm ratio is 2/256 0 0 0 0 0 0 1 0 port pwm ratio is 3/256 0 0 0 0 0 0 1 1 ? port pwm ratio is 252/256 1 1 1 1 1 1 0 0 port pwm ratio is 253/256 1 1 1 1 1 1 0 1 port pwm ratio is 254/256 1 1 1 1 1 1 1 0 port pwm ratio is 256/256 (100% duty cycle) 1 1 1 1 1 1 1 1 register bit description value function default value d[7:6] dont care 00 00 d5 common pwm 0 port uses individual pwm intensity register to set the pwm ratio 0 1 port uses common pwm intensity register to set the pwm ratio d[4:2] blink period 000 port does not blink 000 001 port blink period is 256ms 010 port blink period is 512ms 011 port blink period is 1024ms 100 port blink period is 2048ms 101 port blink period is 4096ms 110/111 undefined d[1:0] blink-on time 00 led is on for 50% of the blink period 00 01 led is on for 25% of the blink period 10 led is on for 12.5% of the blink period 11 led is on for 6.25% of the blink period
???????????????????????????????????????????????????????????????? maxim integrated products 33 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 31. interrupt mask 1 register (0x58) table 32. interrupt mask 2 register (0x59) register bit description value function default value d7 row7 0 interrupt is not masked 1 1 interrupt is masked d6 row6 0 interrupt is not masked 1 1 interrupt is masked d5 row5 0 interrupt is not masked 1 1 interrupt is masked d4 row4 0 interrupt is not masked 1 1 interrupt is masked d3 row3 0 interrupt is not masked 1 1 interrupt is masked d2 row2 0 interrupt is not masked 1 1 interrupt is masked d1 row1 0 interrupt is not masked 1 1 interrupt is masked d0 row0 0 interrupt is not masked 1 1 interrupt is masked register bit description value function default value d7 col7 0 interrupt is not masked 1 1 interrupt is masked d6 col6 0 interrupt is not masked 1 1 interrupt is masked d5 col5 0 interrupt is not masked 1 1 interrupt is masked d4 col4 0 interrupt is not masked 1 1 interrupt is masked d3 col3 0 interrupt is not masked 1 1 interrupt is masked d2 col2 0 interrupt is not masked 1 1 interrupt is masked d1 col1 0 interrupt is not masked 1 1 interrupt is masked d0 col0 0 interrupt is not masked 1 1 interrupt is masked
???????????????????????????????????????????????????????????????? maxim integrated products 34 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection table 33. gpi trigger mode 1 register (0x5a) table 34. gpi trigger mode 2 register (0x5b) register bit description value function default value d7 row7 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d6 row6 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d5 row5 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d4 row4 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d3 row3 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d2 row2 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d1 row1 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d0 row0 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts register bit description value function default value d7 col7 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d6 col6 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d5 col5 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d4 col4 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d3 col3 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d2 col2 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d1 col1 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts d0 col0 0 rising-edge-triggered interrupts 0 1 rising- and falling-edge-triggered interrupts
???????????????????????????????????????????????????????????????? maxim integrated products 35 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection typical application circuit key 7 key 15 key 23 key 31 key 6 key 14 key 22 key 30 key 5 key 13 key 21 key 29 key 4 key 12 key 20 key 28 key 3 key 11 key 19 key 27 key 2 key 10 key 18 key 26 key 1 key 9 key 17 key 25 key 0 key 8 key 16 key 24 i/ o i/ o i/ o col5 col4 col3 col2 col1 col0 row7 row6 row5 row4 row3 row2 row1 row0 col6 col7 +5v +1.8v v cc +2.6v v la +3.3v v cc sda gnd scl c int sda scl int gnd ad0 max7370
???????????????????????????????????????????????????????????????? maxim integrated products 36 max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed. pad. ** future productcontact factory for availability. chip information process: bicmos wafer-level packaging (wlp) applications information for the latest application details on wlp construction, dimensions, tape-carrier information, pcb techniques, bump-pad layout, and recommended reflow tempera - ture profile, as well as the latest information on reli - ability testing results, refer to application note 1891: wafer-level packaging (wlp) and its applications , available at www.maxim-ic.com. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package MAX7370ETG+ -40n c to +85nc 24 tqfn-ep* max7370ewa+** -40n c to +85nc 25 wlp package type package code outline no. land pattern no. 24 tqfn-ep t243a3+1 21-0188 90-0122 25 wlp w252f2+1 21-0453 refer to application note 1891
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 37 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max7370 8 x 8 key-switch controller and led driver/gpios with i 2 c interface and high level of esd protection revision history revision number revision date description pages changed 0 6/11 initial release

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